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David Galbi Phones & Addresses

  • Fremont, CA
  • San Jose, CA
  • Sunnyvale, CA
  • Santa Clara, CA
  • Mountain View, CA
  • 5715 Oleander Cmn, Fremont, CA 94555 (510) 847-1498

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Emails

Publications

Us Patents

Increased Effective Flip-Flop Density In A Structured Asic

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US Patent:
7461365, Dec 2, 2008
Filed:
Jul 10, 2006
Appl. No.:
11/456219
Inventors:
David Galbi - Fremont CA, US
Eric T. West - San Jose CA, US
Assignee:
Lightspeed Logic, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 16, 716 17, 716 18, 716 1
Abstract:
An H-tree is formed in a conducting layer over a base array of a structured ASIC, an H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, each individual flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Increased Effective Flip-Flop Density In A Structured Asic

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US Patent:
8176458, May 8, 2012
Filed:
Dec 1, 2008
Appl. No.:
12/325629
Inventors:
David Galbi - Fremont CA, US
Eric T. West - San Jose CA, US
Assignee:
Otrsotech, Limited Liability Company - Wilmington DE
International Classification:
G06F 17/50
US Classification:
716132, 716118, 716135
Abstract:
An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Method And Structure For Degrouping Mpeg Audio Codes

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US Patent:
58054880, Sep 8, 1998
Filed:
Oct 26, 1995
Appl. No.:
8/548930
Inventors:
David E. Galbi - Sunnyvale CA
Assignee:
C-Cube Microsystems Inc. - Milpitas CA
International Classification:
G06F 752
US Classification:
364764
Abstract:
An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. The decoder includes a degrouping circuit which performs two divisions in three clock cycles to degroup a subband code. Three cycles matches the write time of three components so that subband codes are degrouped and written to memory with a minimum delay. Performing two divides in three clock cycles allows the divider to be smaller and the decoder to be less expensive.

Error Handling Process For Mpeg Decoder

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US Patent:
57682925, Jun 16, 1998
Filed:
Oct 26, 1995
Appl. No.:
8/548768
Inventors:
David E. Galbi - Sunnyvale CA
Assignee:
C-Cube Microsystems, Inc. - Milpitas CA
International Classification:
H04L 100
US Classification:
371 31
Abstract:
In response to an error signal from a source of an MPEG audio data stream, a decoder replaces data with an error code and temporarily enables error handling. The error code is a valid bit combination rarely found in MPEG audio data frames. During audio decoding with error handling enabled, the decoder checks for the error code and replaces the error code with reconstructed data. Typically, some subband data are replaced with zeros so that an error only changes some of the frequency components.

Decoder For Compressed Video Signals

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US Patent:
58704973, Feb 9, 1999
Filed:
May 28, 1992
Appl. No.:
7/891507
Inventors:
David E. Galbi - San Jose CA
Stephen C. Purcell - Mountain View CA
Eric Chi-Wang Chai - Sunnyvale CA
Assignee:
C-Cube Microsystems - Milpitas CA
International Classification:
G06K 936
US Classification:
382232
Abstract:
A decoder for compressed video signals comprises a central processing unit (CPU), a dynamic random access memory (DRAM) controller, a variable length code (VLC) decoder, a pixel filter and a video output unit. The microcoded CPU performs dequantization and inverse cosine transform using a pipelined data path, which includes both general purpose and special purpose hardware. In one embodiment, the VLC decoder is implemented as a table-driven state machine where the table contains both control information and decoded values.

Prenormalization For A Floating-Point Adder

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US Patent:
50105086, Apr 23, 1991
Filed:
Feb 14, 1989
Appl. No.:
7/311294
Inventors:
Hon P. Sit - Fremont CA
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 501
G06F 750
US Classification:
364748
Abstract:
In a floating-point subtraction of two numbers where a normalized result is needed, a prenormalization circuit predicts the number of leading zeroes which will appear in the resultant mantissa, due to the close value of the two source operands. The prenormalization circuit then causes appropriate left shifts of the two operand mantissas prior to the subtraction (two's complement addition) is performed, wherein the resultant mantissa will already be normalized.

Method For Decoding Mpeg Audio Data

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US Patent:
58648178, Jan 26, 1999
Filed:
Oct 26, 1995
Appl. No.:
8/548895
Inventors:
David E. Galbi - Sunnyvale CA
Assignee:
C-Cube Microsystems Inc. - Milpitas CA
International Classification:
G10L 302
US Classification:
704503
Abstract:
An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increase throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller.

Mpeg Audio/Video Decoder

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US Patent:
56490291, Jul 15, 1997
Filed:
Sep 23, 1994
Appl. No.:
8/311659
Inventors:
David E. Galbi - Sunnyvale CA
International Classification:
G06K 936
US Classification:
382233
Abstract:
An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increases throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller. The decoder includes a degrouping circuit which performs two divisions in three clock cycles to degroup a subband code. Three cycles matches the write time of three components so that subband codes are degrouped and written to memory with a minimum delay. Performing two divides in three clock cycles allows the divider to be smaller.
David E Galbi from Fremont, CA, age ~60 Get Report