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David Galbi Phones & Addresses

  • Fremont, CA
  • San Jose, CA
  • Sunnyvale, CA
  • Santa Clara, CA
  • Mountain View, CA
  • 5715 Oleander Cmn, Fremont, CA 94555 (510) 847-1498

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Emails

Publications

Us Patents

Increased Effective Flip-Flop Density In A Structured Asic

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US Patent:
7461365, Dec 2, 2008
Filed:
Jul 10, 2006
Appl. No.:
11/456219
Inventors:
David Galbi - Fremont CA,
Eric T. West - San Jose CA,
Assignee:
Lightspeed Logic, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 16, 716 17, 716 18, 716 1
Abstract:
An H-tree is formed in a conducting layer over a base array of a structured ASIC, an H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, each individual flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Mpeg Video Decompression Processor

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US Patent:
5598483, Jan 28, 1997
Filed:
Oct 24, 1994
Appl. No.:
8/297722
Inventors:
Stephen C. Purcell - Mountain View CA
David E. Galbi - Santa Clara CA
Frank H. Liao - Sunnyvale CA
Yvonne C. Tse - Fremont CA
Assignee:
C-Cube Microsystems, Inc. - Milpitas CA
International Classification:
G06K 936
US Classification:
382232
Abstract:
A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the present invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the present invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the present invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors.

Decompression Processor For Video Applications

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US Patent:
5815646, Sep 29, 1998
Filed:
Oct 11, 1994
Appl. No.:
8/296387
Inventors:
Stephen C. Purcell - Mountain View CA
David E. Galbi - Santa Clara CA
Frank H. Liao - Sunnyvale CA
Yvonne C. Tse - Fremont CA
Assignee:
C-Cube Microsystems - Milpitas CA
International Classification:
G06F 1516
US Classification:
395163
Abstract:
A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920. times. 1080 pixel display space is divided into four vertical sections of 480. times. 1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240. times. 1080 pixels. Each decompression structure decodes a 480. times. 1088-pixel picture area with access to up to two additional 240. times. 1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8. times.

Sticky Bit Predictor For Floating-Point Multiplication

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US Patent:
4928259, May 22, 1990
Filed:
Sep 23, 1988
Appl. No.:
7/248740
Inventors:
David Galbi - Mountain View CA
Les Kohn - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 738
G06F 752
US Classification:
364745
Abstract:
In a floating-point multiplication of two numbers in which a value of a sticky bit is needed, each of two trailing zero encoders calculates the number of trailing zeroes associated with its mantissa. The sum of the two trailing zero counts determines the number of trailing zeroes in the mantissa product. This sum is compared to a constant to determine the sticky bit. Each encoder is comprised of a plurality of individual encoders arranged in a plurality of rows for providing the trailing zero count.

Circuit For Adding/Subtracting Two Floating Point Operands

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US Patent:
5027308, Jun 25, 1991
Filed:
Feb 14, 1989
Appl. No.:
7/311296
Inventors:
Hon P. Sit - Fremont CA
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 738
G06F 700
US Classification:
364748
Abstract:
In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa not to be normalized. A dual adder scheme is used to always provide a normalized result. One adder provides an unshifted result while the second adder provides a shifted result. A logic circuit looks for a carry out when performing addition and a bit value of the msb when performing subtraction to select the output from the adder providing the proper normalization. Rounding logic circuitry is used to predict the rounding of the resultant mantissa and carry bits are coupled as a carry-in to the adders to achieve the proper rounding in the same clock cycle as the adding/subtracting of the two mantissas.

Four-To-Two Adder Cell For Parallel Multiplication

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US Patent:
4901270, Feb 13, 1990
Filed:
Sep 23, 1988
Appl. No.:
7/248797
Inventors:
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 750
G06F 752
US Classification:
364786
Abstract:
A four-to-two adder for adding four numbers and generating two numbers which has the same sum as the sum of the four input numbers is used to add partial products in a multiplier. A plurality of adder cells are arranged in parallel to process corresponding bits of the four numbers. Each adder cell couples three of the four input bits to the next stage. A four-bit parity circuit is used to control two multiplexers which select signals from a carry generator and the one input signal which is not coupled to the subsequent adder cell stage to provide two output bits corresponding to the two output numbers.

Method And Apparatus For Mapping Data Of A 2-Dimensional Space From A Linearly Addressed Memory System

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US Patent:
5608888, Mar 4, 1997
Filed:
Aug 26, 1994
Appl. No.:
8/296943
Inventors:
Stephen C. Purcell - Mountain View CA
David E. Galbi - Santa Clara CA
Frank H. Liao - Sunnyvale CA
Yvonne C. Tse - Fremont CA
Assignee:
C-Cube Microsystems, Inc. - Milpitas CA
International Classification:
G06F 1200
US Classification:
395412
Abstract:
A 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel. times. 2 pixel "quad pixel" configuration, or in a 4 pixel. times. 1 pixel horizontal "scan" configuration. In addition, a structure and a method are provided for accessing a 16. times. 16-pixel picture area in two parts, in order that the number of DRAM page boundaries crossed during access of the 16. times. 16-pixel picture area is minimized, thereby increasing the efficiency of memory access by reducing the overhead cost of initial accesses under page mode access to DRAMs.

System For Providing Antialiased Video Overlays

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US Patent:
5568167, Oct 22, 1996
Filed:
Sep 23, 1994
Appl. No.:
8/311670
Inventors:
David E. Galbi - Sunnyvale CA
Stephen C. Purcell - Mountain View CA
Assignee:
C-Cube Microsystems, Inc. - Milpitas CA
International Classification:
H04N 974
US Classification:
348589
Abstract:
A separate data stream allows encoding of an overlay image, which is to be superimposed on images of a video sequence. The pixels of the overlay image can be transparent or have a text color, a shadow color, or an intermediate color either between the text color and the shadow color, or between the shadow color and the color of the corresponding pixel in the underlying video image. The intermediate colors provide for antialiasing. In addition, a color selection circuit allows selection of the next color from a pool of 9 colors, using a 3-bit field.
David E Galbi from Fremont, CA, age ~58 Get Report