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Kamran Iravani Phones & Addresses

  • 2400 Cristo Rey Pl, Los Altos, CA 94024
  • Lake Oswego, OR
  • Clackamas, OR
  • San Jose, CA
  • Cupertino, CA
  • Santa Clara, CA
  • Sherman Oaks, CA
  • 2400 Cristo Rey Pl, Los Altos, CA 94024 (650) 451-9177

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Resumes

Resumes

Kamran Iravani Photo 1

President And Chief Technology Officer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Pico Semiconductor
President and Chief Technology Officer
Skills:
Ic
Pll
Serdes
Low Power Design
Asic
Semiconductors
Pcie
Oscillators
Mixed Signal
Sata
Electronics
Analog Circuit Design
Cmos
Vlsi
Analog
Fpga
Soc
Semiconductor Industry
Testing
Eda
Algorithms
Engineering Management
Signal Integrity
Kamran Iravani Photo 2

Kamran Iravani

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Work:
Pico Semiconductor Inc
President, Chief Technology Officer

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kamran Iravani
President
PICO SEMICONDUCTOR INC
Business Services at Non-Commercial Site
2400 Cristo Rey Pl, Los Altos, CA 94024
Kamran Iravani
UNIGATE SEMICONDUCTOR, LLC
Ste 10 STE 100, Tucson, AZ 85755
2400 Cristo Rev Pl, Los Altos, CA 94024
Kamran Iravani
Chief Technology Officer
Taracom Corp
Commercial Physical Research
3375 Scott Blvd, Santa Clara, CA 95054
(408) 486-9700

Publications

Us Patents

Vco Circuit Using Negative Feedback To Reduce Phase Noise

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US Patent:
6353368, Mar 5, 2002
Filed:
Nov 9, 1999
Appl. No.:
09/437576
Inventors:
Kamran Iravani - San Jose CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H03B 524
US Classification:
331 57, 331 8, 331 17, 331 1 R, 331 1 A, 331 25, 331 34, 327 39, 327155
Abstract:
A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO output signal. The frequency to voltage converter converts a frequency of the VCO output signal into a corresponding voltage output. The voltage output is coupled to control the bias circuit. The VCO cell includes a current source coupled to the bias circuit such that the voltage output from the voltage a current converter provides negative feedback to the VCO cell via the current source. The negative feedback, in turn, reduces the phase noise on the VCO output signal.

Pll With Low Spurs

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US Patent:
7541850, Jun 2, 2009
Filed:
May 16, 2007
Appl. No.:
11/804169
Inventors:
Kamran Iravani - Los Altos CA, US
Assignee:
PICO Semiconductor, Inc. - Los Altos CA
International Classification:
H03L 7/06
US Classification:
327156, 327147
Abstract:
A PLL circuit having a low spur output. The PLL circuit includes a PFD (Phase-Frequency Detector), a charge-pump coupled to the PFD, an SCR (switch-capacitor resistor) coupled to the charge pump, a filter coupled to the SCR, and a VCO circuit coupled to the filter, wherein the SCR reduces an amplitude of a plurality of current pulses at an output of the charge-pump before the plurality of current pulses reach an input of the VCL circuit.

Wide Range/High Speed Low Power Cmos Vco

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US Patent:
7863991, Jan 4, 2011
Filed:
Oct 6, 2008
Appl. No.:
12/246429
Inventors:
Kamran Iravani - Los Altos CA, US
Assignee:
Pico Semiconductor, Inc. - Los Altos CA
International Classification:
H03K 3/03
US Classification:
331 57, 331177 R
Abstract:
A VCO circuit having low jitter and low PSS (power supply sensitivity). The VCO circuit includes a first ring oscillator stage, a second ring oscillator stage coupled to the first ring oscillator stage, and a VCO input coupled to both the first ring oscillator stage and the second ring oscillator stage for receiving a control voltage. Each of the first ring oscillator stage and the second ring oscillator stage further includes a CMOS inverter with a plurality of cross coupled transistors to implement oscillation of the VCO circuit.

Nominal Temperature And Process Compensating Bias Circuit

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US Patent:
59492775, Sep 7, 1999
Filed:
Oct 20, 1997
Appl. No.:
8/954571
Inventors:
Kamran Iravani - San Jose CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G05F 302
US Classification:
327541
Abstract:
The present invention provides a nominal temperature and process compensating bias circuit for an integrated circuit. The bias circuit comprises a current source, a pair of linear devices, and a current stage. The current source generates a bias current. The pair of linear devices includes a first linear device and a second linear device. The first and second linear devices are coupled to each other and to the current source at a common node to enable the bias current from the current source to flow through the linear devices. The current stage includes a first transistor and a second transistor with the first transistor being coupled to the first linear device at the drain node of the first transistor and the second transistor being coupled to the second linear device at the drain node of the second transistor. In this configuration, the first and the second transistors have different channel width (W) to channel length (L) ratios such that the transistor with a larger W to L ratio conducts more current than the transistor with smaller W to L ratio to generate a voltage at the drain of the transistor with larger W to L ratio, thereby counteracting variations in temperature and process in the integrated circuit.

Differential Mos Current-Mode Logic Circuit Having High Gain And Fast Speed

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US Patent:
59778008, Nov 2, 1999
Filed:
Oct 20, 1997
Appl. No.:
8/955012
Inventors:
Kamran Iravani - San Jose CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H03K 19094
US Classification:
326115
Abstract:
The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance. Hence, the present invention allows faster charging and discharging of transistors, which results in faster switching transistors and higher speed circuit.

Vco Circuit Having Low Gain Variation Over Different Processes And Operating Temperatures And Having Low Power Supply Noise Sensitivity

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US Patent:
59735732, Oct 26, 1999
Filed:
Nov 18, 1997
Appl. No.:
8/972838
Inventors:
Kamran Iravani - San Jose CA
Gary Miller - Corbett OR
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H03B 524
H03B 504
US Classification:
331 57
Abstract:
A voltage controlled oscillator (VCO) circuit having low sensitivity to fabrication process variation, operating temperature variation, and power supply noise. The circuit of the present invention includes a current source controller, a bias circuit, and a first and second VCO cell. The first and second VCO cells are coupled to each other and are coupled to the bias circuit. The VCO circuit of the present invention also includes a VCO output for transmitting a VCO output signal to external electronics. A bias circuit current source is coupled to the bias circuit to transmit a bias circuit current from a power supply to the bias circuit. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell. The bias circuit current source, the first current source, and the second current source are each coupled to the current source controller to increase the power supply rejection ratio of the VCO circuit of the present invention.

Vco Having A Low Sensitivity To Noise On The Power Supply

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US Patent:
59949686, Nov 30, 1999
Filed:
Nov 18, 1997
Appl. No.:
8/972771
Inventors:
Kamran Iravani - San Jose CA
Gary Miller - Corbett OR
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H03L 7099
H03B 502
US Classification:
331 57
Abstract:
The present invention comprises a voltage controlled oscillator (VCO) circuit having high power supply noise rejection. The VCO circuit includes a VCO input for receiving a control voltage. A level shifter circuit is coupled to the VCO input. A first and second VCO cell are coupled to the level shifter circuit and are coupled to each other. The VCO circuit also includes a VCO output for transmitting a VCO output signal. A first source follower transistor is coupled to the first VCO cell to transmit a first voltage from the power supply to the first VCO cell. A second source follower transistor is coupled to the second VCO cell to transmit a second voltage from the power supply to the second VCO cell. A first and second load transistor are included in each VCO cell. They are directly coupled to receive the control voltage such that the VCO output signal is less sensitive to noise on the power supply and the VCO output signal remains stable.

Vco In Cmos Technology Having An Operating Frequency Of 3 Ghz And Greater

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US Patent:
59364769, Aug 10, 1999
Filed:
Nov 18, 1997
Appl. No.:
8/972374
Inventors:
Kamran Iravani - San Jose CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H03B 504
US Classification:
331 57
Abstract:
A CMOS super high speed voltage controlled oscillator (VCO) circuit that operates at frequencies of at least 3 GHz. The VCO circuit of the present invention includes a replica circuit, a first VCO cell coupled to the replica circuit, and a second VCO cell coupled to the first VCO cell and the replica circuit. A VCO output for transmitting a VCO output signal is also included. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell. The first VCO cell and the second VCO cell each have respective first and second source follower load transistors coupled to the replica circuit. In addition, the first and second VCO cells, the first and second current sources, and the replica circuit are all fabricated using n-channel MOS transistors. Consequently, the VCO circuit of the present invention reliably oscillates at 3 GHz or above and produces a VCO output having a frequency of 3 GHz or above.
Kamran Iravani from Los Altos, CA, age ~58 Get Report