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Mahesh Maddury Phones & Addresses

  • 5822 Chambertin Dr, San Jose, CA 95118 (408) 723-4143
  • 2985 Aurora Ave, Boulder, CO 80303
  • 112 Esplanade Ave, Pacifica, CA 94044 (650) 738-3525
  • 580 Mill Creek Ln, Santa Clara, CA 95054 (408) 567-9961
  • San Francisco, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mahesh Maddury
President
Bitforth Inc
Business Services at Non-Commercial Site
830 Stewart Dr, Sunnyvale, CA 94085
1050 Kristen Ct, San Jose, CA 95120

Publications

Us Patents

Method And Apparatus For Accelerating Preliminary Operations For Cryptographic Processing

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US Patent:
7187770, Mar 6, 2007
Filed:
Jul 16, 2002
Appl. No.:
10/196829
Inventors:
Mahesh S. Maddury - Santa Clara CA,
Kenneth J. Tomei - Sunnyvale CA,
Justina Provine - San Jose CA,
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04K 1/00
G06F 17/00
US Classification:
380 28, 708490
Abstract:
A method and apparatus for cryptographic data processing, includes determining a first modulus having up to a first number of binary digits. A large integer is received which has up to a second number of binary digits that is greater than the first number of binary digits. The first modulus and the large integer are sent to a first processor for computing a first residue of the large integer modulo the first modulus. Before the first processor finishes computing the first residue, the first modulus is also sent to a second processor for computing a second residue of two raised to a power of twice the first number of binary digits modulo the first modulus. The first residue and the second residue are used as input to a third processor that computes a cryptographic result based on the large integer.

Method And Apparatus For Calculating A Multiplicative Inverse Of An Element Of A Prime Field

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US Patent:
7191333, Mar 13, 2007
Filed:
Oct 25, 2001
Appl. No.:
10/040050
Inventors:
Mahesh S. Maddury - Santa Clara CA,
Kenneth J. Tomei - Sunnyvale CA,
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H03K 19/00
G06F 7/04
G06F 7/556
US Classification:
713174, 713176, 713180, 726 6, 726 17
Abstract:
Techniques for implementing a digital signature algorithm in electronic computer hardware include computing the multiplicative inverse of a particular integer modulo a prime modulus by computing a first quantity modulo the prime modulus. The first quantity substantially equals, modulo the prime modulus, the particular integer raised to a power of a second quantity. The second quantity is two less than the prime modulus. The techniques allow an integrated circuit block to compute a modulo multiplicative inverse, such as for signing and verifying digital signatures, using existing blocks of circuitry that consume considerably less area on a chip, and incur fewer developmental costs, than an implementation of an algorithm conventionally used in software.

Digital Circuit Apparatus And Method For Accelerating Preliminary Operations For Cryptographic Processing

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US Patent:
7319750, Jan 15, 2008
Filed:
Aug 5, 2002
Appl. No.:
10/212936
Inventors:
Mahesh S. Maddury - Santa Clara CA,
Kenneth J. Tomei - Sunnyvale CA,
Justina Provine - San Jose CA,
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04K 1/00
G06F 17/00
US Classification:
380 28, 708490
Abstract:
A digital circuit apparatus and method for cryptographic data processing includes steps and means for determining a first modulus having up to a first number of binary digits. A large integer is received which has up to a second number of binary digits that is greater than the first number of binary digits. The first modulus and the large integer are sent to a first processor for computing a first residue of the large integer modulo the first modulus. Before the first processor finishes computing the first residue, the first modulus is also sent to a second processor for computing a second residue of two raised to a power of twice the first number of binary digits modulo the first modulus. The first residue and the second residue are used as input to a third processor that computes a cryptographic result based on the large integer.

Forwarding Multi-Destination Packets In A Network With Virtual Port Channels

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US Patent:
8249069, Aug 21, 2012
Filed:
Mar 30, 2010
Appl. No.:
12/798131
Inventors:
Pirabhu Raman - San Jose CA,
Dinesh Dutt - Sunnyvale CA,
Mahesh Maddury - San Jose CA,
Subbarao Arumilli - Santa Clara CA,
Vijay Rangarajan - Fremont CA,
Ray Kloth - Saratoga CA,
Sanjay Sane - Fremont CA,
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 12/28
US Classification:
370390, 370401
Abstract:
In one embodiment, a method includes receiving a multi-destination packet at a switch in communication with a plurality of servers through a network device, identifying a port receiving the multi-destination packet at the switch or a forwarding topology for the multi-destination packet, selecting a bit value based on the identified port or forwarding topology, inserting the bit value into a field in a virtual network tag in the multi-destination packet, and forwarding the multi-destination packet with the virtual network tag to the network device. The network device is configured to forward the multi-destination packet to one or more of the servers based on the bit value in the multi-destination packet. An apparatus for forwarding multi-destination packets is also disclosed.

Longest Prefix Match Scheme

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US Patent:
2013003, Jan 31, 2013
Filed:
Oct 28, 2011
Appl. No.:
13/284829
Inventors:
Jian Liu - Palo Alto CA,
Philip Lynn Leichty - Rochester MN,
How Tung Lim - San Jose CA,
John Michael Terry - San Jose CA,
Mahesh Srinivasa Maddury - San Jose CA,
Wing Cheung - Fremont CA,
Kung Ling Ko - Union City CA,
Assignee:
Brocade Communications Systems, Inc. - San Jose CA
International Classification:
G06F 17/30
US Classification:
707706, 707E17108
Abstract:
A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.

Reverse Path Forwarding Lookup With Link Bundles

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US Patent:
2013003, Feb 7, 2013
Filed:
Aug 3, 2011
Appl. No.:
13/136516
Inventors:
Sarang Dharmapurikar - Sant Clara CA,
Mahesh Maddury - San Jose CA,
Francisco Matus - Saratoga CA,
Assignee:
CISCO TECHNOLOGY, INC. - San Jose CA
International Classification:
H04L 12/56
US Classification:
370390, 370389
Abstract:
In one embodiment, a method includes receiving a packet at an interface at a network device having a plurality of interfaces connected to a plurality of links forming a bundle, performing a Reverse Path Forwarding (RPF) check on the received packet, and forwarding the packet if it passes the RPF check. The RPF check includes a lookup in an RPF table having a plurality of entries for the bundle, each of the entries including the bundle and one of the links in the bundle, and verification that the interface receiving the packet is connected to one of the links in the bundle identified in the lookup. An apparatus is also disclosed.

Packet Forwarding Using An Approximate Ingress Table And An Exact Egress Table

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US Patent:
2013006, Mar 14, 2013
Filed:
Sep 12, 2011
Appl. No.:
13/229894
Inventors:
Sarang Dharmapurikar - Santa Clara CA,
Kit Chiu Chu - Fremont CA,
Mahesh Maddury - San Jose CA,
Dinesh G. Dutt - Sunnyvale CA,
Francisco Matus - Saratoga CA,
Assignee:
CISCO TECHNOLOGY, INC. - San Jose CA
International Classification:
H04L 12/56
US Classification:
370392, 370401
Abstract:
Techniques are provided for forwarding packets via an intermediate network device. A packet comprising a destination MAC address is received at a first port of a network device having a plurality of bi-directional ports. A second port of the network device to which the packet should be forwarded is identified through the use of at least an approximate ingress table at the first port comprising a plurality of compressed destination MAC addresses each having an associated egress port, and the packet is forwarded to the second port. At the second port, a subsequent network device to which the packet should be forwarded is identified through the use of an exact egress table at the second port including exact destination MAC addresses each associated with a network device connected to the second port, and the packet is forwarded to the subsequent network device.

Residue Number System Based Pre-Computation And Dual-Pass Arithmetic Modular Operation Approach To Implement Encryption Protocols Efficiently In Electronic Integrated Circuits

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US Patent:
7027598, Apr 11, 2006
Filed:
Sep 19, 2001
Appl. No.:
09/956732
Inventors:
Mihailo M. Stojancic - Cary NC,
Mahesh S. Maddury - Santa Clara CA,
Kenneth J. Tomei - Sunnyvale CA,
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04K 1/00
H04L 9/00
US Classification:
380 28, 708103, 708135, 708200, 708490, 708501, 708502, 708503, 708504, 708505, 708523, 708524, 713174
Abstract:
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.
Mahesh S Maddury from San Jose, CA, age ~46 Get Report