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Michael Rifani Phones & Addresses

  • 16730 SW Whitetail Ln, Beaverton, OR 97007
  • 2781 NW Overlook Dr #418, Hillsboro, OR 97124
  • 630 Young Grad House, West Lafayette, IN 47906
  • 210 E Wood St, West Lafayette, IN 47906 (317) 743-5582
  • 201 W Wood St #3, West Lafayette, IN 47906
  • 4128 Vesta St, Portland, OR 97219
  • Tigard, OR
  • W Lafayette, IN

Work

Company: Intel Oct 1998 to 2012 Position: Senior component design engineer

Education

Degree: Ph.D. School / High School: Purdue University 1993 to 1998 Specialities: Electrical Engineering

Languages

Indonesian • Malay

Industries

Semiconductors

Resumes

Resumes

Michael Rifani Photo 1

Senior Design Engineer At Intel Corporation

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Position:
Senior Component Design Engineer at Intel
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Intel since Oct 1998
Senior Component Design Engineer
Education:
Purdue University 1993 - 1998
Ph.D., Electrical Engineering
Languages:
Indonesian
Malay

Publications

Us Patents

Closed-Loop Independent Dll-Controlled Rise/Fall Time Control Circuit

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US Patent:
7038512, May 2, 2006
Filed:
Jun 29, 2004
Appl. No.:
10/877991
Inventors:
Timothy M Wilson - Aloha OR,
Michael C. Rifani - Portland OR,
Songmin Kim - Beaverton OR,
Greg Taylor - Portland OR,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5/12
US Classification:
327170, 327112
Abstract:
A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

Closed-Loop Independent Dll-Controlled Rise/Fall Time Control Circuit

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US Patent:
7038513, May 2, 2006
Filed:
Jun 29, 2004
Appl. No.:
10/878033
Inventors:
Timothy M. Wilson - Aloha OR,
Michael C. Rifani - Portland OR,
Songmin Kim - Beaverton OR,
Greg Taylor - Portland OR,
Navindra Navaratnam - Hillsboro OR,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5/12
US Classification:
327170, 327112
Abstract:
A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

Phase Jitter Measurement Circuit

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US Patent:
7308372, Dec 11, 2007
Filed:
Jan 26, 2006
Appl. No.:
11/341781
Inventors:
Michael C. Rifani - Portland OR,
Keng L. Wong - Portland OR,
Christopher Pan - Portland OR,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 29/02
H03L 7/06
US Classification:
702 69, 702 72, 702 74, 702 79, 702 89, 702178, 702189, 327149, 327158, 327270
Abstract:
A method, an apparatus, and a system for phase jitter measurement circuits are described herein.

Controlling Sequence Of Clock Distribution To Clock Distribution Domains

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US Patent:
7386749, Jun 10, 2008
Filed:
Mar 4, 2005
Appl. No.:
11/073294
Inventors:
Michael C. Rifani - Beaverton OR,
Vaughn J. Grossnickle - Beaverton OR,
Keng L. Wong - Portland OR,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/12
G06F 1/14
G06F 1/00
US Classification:
713400, 713502, 713322
Abstract:
An embodiment of the present invention is a technique to control clock distribution to a circuit. A scheduler schedules a sequence of a clock distribution of clock signals to a plurality of clock distribution domains (CKDOMs) in the circuit according to a state status of the circuit. A controller controls enabling the clock distribution to the CKDOMs according to the scheduled sequence.

Delay Element Calibration

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US Patent:
2005027, Dec 15, 2005
Filed:
May 27, 2004
Appl. No.:
10/856907
Inventors:
Michael Rifani - Portland OR,
Keng Wong - Portland OR,
Christopher Pan - Portland OR,
International Classification:
G01R029/02
US Classification:
702079000
Abstract:
An apparatus and method for calibrating a delay element is described herein.

Phase Locked Loop Circuit

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US Patent:
2007015, Jul 12, 2007
Filed:
Dec 27, 2005
Appl. No.:
11/319043
Inventors:
Feng Wang - Portland OR,
Keng Wong - Portland OR,
Michael Rifani - Beaverton OR,
International Classification:
H03L 7/06
US Classification:
327156000
Abstract:
A technique includes locking a locked loop circuit onto a reference clock signal. The locking includes locking the lock loop circuit onto the reference clock signal in response to a first feedback signal provided by a first feedback path and locking the locked loop circuit onto the reference clock signal in response to a second feedback signal that is provided by a second feedback path.

Data Transfer Between Asynchronous Clock Domains

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US Patent:
2013025, Sep 26, 2013
Filed:
Dec 28, 2011
Appl. No.:
13/991602
Inventors:
Michael C. Rifani - Beaverton OR,
Alan B. Kyker - Winters CA,
Alan S. Geist - Portland OR,
David M. Lee - Portland OR,
International Classification:
G06F 1/12
US Classification:
713400
Abstract:
Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.
Michael C Rifani from Beaverton, OR, age ~52 Get Report