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Nathan Hiltebeitel Phones & Addresses

  • 740 Carmichael Rd, Owego, NY 13827 (607) 687-6177
  • Essex Junction, VT
  • Candor, NY
  • 740 Carmichael Rd, Owego, NY 13827 (607) 742-2166

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Emails

Publications

Us Patents

Multiplexed Serial Register Architecture For Vram

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US Patent:
49842145, Jan 8, 1991
Filed:
Dec 5, 1989
Appl. No.:
7/446032
Inventors:
Nathan R. Hiltebeitel - South Burlington VT
Robert Tamlyn - Jericho VT
Steven W. Tomashot - Jericho VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 700
G11C 800
US Classification:
36523005
Abstract:
A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

Sam Data Selection On Dual-Ported Dram Devices

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US Patent:
52572374, Oct 26, 1993
Filed:
Nov 12, 1991
Appl. No.:
7/791666
Inventors:
Michael A. Aranda - Saugerties NY
Andrew D. Bowen - Saugerties NY
Timothy J. Ebbers - Shokan NY
Randall L. Henderson - West Hurley NY
Nathan R. Hiltebeitel - Essex Junction VT
Robert Tamlyn - Jericho VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 800
US Classification:
36523005
Abstract:
The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.
Nathan R Hiltebeitel from Owego, NY, age ~58 Get Report