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Shalesh Thusoo

from San Jose, CA
Age ~52

Shalesh Thusoo Phones & Addresses

  • 1818 Shady Grove Ct, San Jose, CA 95138
  • 165 Blossom Hill Rd, San Jose, CA 95123
  • 992 Cameron Cir, Milpitas, CA 95035
  • 716 Arbor Way, Milpitas, CA 95035
  • Sanger, CA
  • Cleveland Heights, OH
  • Fremont, CA

Resumes

Resumes

Shalesh Thusoo Photo 1

Senior Director Extereme Compute Processors And Accelerators Group

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Intel Corporation
Senior Director Extereme Compute Processors and Accelerators Group

Cisco Aug 2001 - Nov 2015
Director, Hardware Engineering

Auroranetics Oct 2000 - Aug 2001
Member of Technical Staff

Ati Technology Sep 1996 - Oct 2000
Senior Design Manager

Exponential Technology Sep 1995 - Sep 1996
Member of Technical Staff
Education:
Case Western Reserve University 1991 - 1992
Masters, Computer Engineering
Wichita State University 1988 - 1990
Bachelors, Electronics Engineering
Skills:
Asic
Debugging
Hardware Architecture
Embedded Systems
Hardware
Ethernet
Verilog
Networking
Fpga
Soc
Tcp/Ip
Switching
Cpu
Arm
Powerpc
Routing
X86
Spark
Processors
Network Processors
Artificial Intelligence
Shalesh Thusoo Photo 2

Shalesh Thusoo

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Location:
San Jose, CA

Publications

Us Patents

Method And Apparatus For Providing Probe Based Bus Locking And Address Locking

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US Patent:
6389519, May 14, 2002
Filed:
Jul 19, 1999
Appl. No.:
09/356732
Inventors:
Shalesh Thusoo - Milpitas CA
Niteen Patkar - Sunnyvale CA
Assignee:
ATI International SRL - Barbados
International Classification:
G06F 1300
US Classification:
711152, 711201, 710200
Abstract:
A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.

Method And Apparatus For Interfacing A Processor With A Bus

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US Patent:
6430646, Aug 6, 2002
Filed:
Aug 18, 1999
Appl. No.:
09/377004
Inventors:
Shalesh Thusoo - Milpitas CA
Niteen Patkar - Sunnyvale CA
Korbin Van Dyke - Sunol CA
Stephen C. Purcell - Mountain View CA
Assignee:
ATI International Srl - Barbados
International Classification:
G06F 1300
US Classification:
710305, 710306, 711100, 711111, 711150
Abstract:
A method and apparatus for interfacing a processor with a bus includes processing that begins by storing transactions initiated by the processor into a buffer. The processing then continues by selecting one of the transactions stored in the buffer and placing the selected transaction on the bus. The processing continues by monitoring progress of fulfillment of each transaction in the buffer and flagging a transaction when it has been successfully completed. The processing also includes processing at least two related transactions prior to selecting one of the transactions from the buffer where, if transactions can be processed locally, they do not need to be transported on the bus. In addition, the processing includes monitoring the bus for related transactions initiated by another processor such that these transactions can be more efficiently processed. The related transaction on the bus would correspond to a transaction queued in the buffer.

Method And Apparatus For Busing Data Elements

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US Patent:
6449671, Sep 10, 2002
Filed:
Jun 9, 1999
Appl. No.:
09/328971
Inventors:
Niteen A. Patkar - Sunnyvale CA
Stephen C. Purcell - Mountain View CA
Shalesh Thusoo - Milpitas CA
Korbin S. Van Dyke - Sunol CA
Assignee:
ATI International Srl
International Classification:
G06F 1300
US Classification:
710107, 710110, 710112
Abstract:
A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.

Multi-Branch Resolution

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US Patent:
6578134, Jun 10, 2003
Filed:
Nov 29, 1999
Appl. No.:
09/451300
Inventors:
Korbin Van Dyke - Sunol CA
Niteen Patkar - Sunnyvale CA
Shalesh Thusoo - Milpitas CA
TR Ramesh - Newark CA
Assignee:
ATI International SRL - Christ Church
International Classification:
G06F 938
US Classification:
712219, 712236, 712239, 712234, 712213
Abstract:
A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.

Method Of Manufacture And Apparatus Of An Integrated Computing System

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US Patent:
6643726, Nov 4, 2003
Filed:
Aug 18, 1999
Appl. No.:
09/376820
Inventors:
Niteen Patkar - Sunnyvale CA
Ali Alasti - Los Altos CA
Don Van Dyke - Pleasanton CA
Korbin Van Dyke - Sunol CA
Shalesh Thusoo - Milpitas CA
Stephen C. Purcell - Mountain View CA
Govind Malalur - Fremont CA
Assignee:
ATI International SRL - Christchurch
International Classification:
G06F 1336
US Classification:
710306
Abstract:
An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e. g. , data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e. g. , internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

Method And Apparatus For Out Of Order Memory Processing Within An In Order Processor

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US Patent:
6775756, Aug 10, 2004
Filed:
Oct 11, 1999
Appl. No.:
09/416196
Inventors:
Shalesh Thusoo - Milpitas CA
Niteen Patkar - Sunnyvale CA
Jim Lin - Sunnyvale CA
Assignee:
ATI International Srl - Barbados
International Classification:
G06F 1200
US Classification:
711169, 711140, 711215, 711214, 712219
Abstract:
A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.

Profiling Program Execution Into Registers Of A Computer

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US Patent:
6826748, Nov 30, 2004
Filed:
Jun 24, 1999
Appl. No.:
09/339749
Inventors:
Paul H. Hohensee - Nashua NH
David L. Reese - Westborough MA
Korbin S. Van Dyke - Sunol CA
T. R. Ramesh - Newark CA
Shalesh Thusoo - Milpitas CA
Gurjeet Singh Saund - Mountain View CA
Niteen Aravind Patkar - Sunnyvale CA
Assignee:
ATI International SRL - Hastings
International Classification:
G06F 944
US Classification:
717130
Abstract:
A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

Exception Mechanism For A Computer

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US Patent:
6934832, Aug 23, 2005
Filed:
Sep 21, 2000
Appl. No.:
09/667226
Inventors:
Korbin S. Van Dyke - Sunol CA, US
Paul Campbell - Oakland CA, US
Shalesh Thusoo - Milpitas CA, US
T. R. Ramesh - Union City CA, US
Alan McNaughton - Belmont CA, US
Assignee:
ATI International SRL - Hastings
International Classification:
G06F011/00
US Classification:
712244
Abstract:
A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers.
Shalesh Thusoo from San Jose, CA, age ~52 Get Report