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Shalesh Thusoo Phones & Addresses

  • 1818 Shady Grove Pl, San Jose, CA 95138
  • 165 Blossom Hill Rd, San Jose, CA 95123
  • 716 Arbor Way, Milpitas, CA 95035
  • Sanger, CA
  • Cleveland Heights, OH
  • Fremont, CA

Industries

Computer Hardware

Resumes

Resumes

Shalesh Thusoo Photo 1

Shalesh Thusoo

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Location:
San Jose, California
Industry:
Computer Hardware

Publications

Us Patents

Method And Apparatus For Providing Probe Based Bus Locking And Address Locking

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US Patent:
6389519, May 14, 2002
Filed:
Jul 19, 1999
Appl. No.:
09/356732
Inventors:
Shalesh Thusoo - Milpitas CA
Niteen Patkar - Sunnyvale CA
Assignee:
ATI International SRL - Barbados
International Classification:
G06F 1300
US Classification:
711152, 711201, 710200
Abstract:
A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.

Area Efficient Bist System For Memories

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US Patent:
7240255, Jul 3, 2007
Filed:
Mar 22, 2005
Appl. No.:
11/088636
Inventors:
Charles Akum Njinda - San Jose CA,
Shalesh Thusoo - Milpitas CA,
Hao Wang - San Jose CA,
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G11C 29/00
US Classification:
714718, 714733
Abstract:
A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with the particular DAL.

Stack Push/Pop Tracking And Pairing In A Pipelined Processor

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US Patent:
5687336, Nov 11, 1997
Filed:
Jan 11, 1996
Appl. No.:
8/584836
Inventors:
Gene Shen - Mountain View CA
Shalesh Thusoo - Milpitas CA
James S. Blomgren - San Jose CA
Assignee:
Exponential Technology, Inc. - San Jose CA
International Classification:
G06F 932
US Classification:
395378
Abstract:
A pipelined processor executes several stack instructions simultaneously. Additional shadow registers for stack pointers of instructions in the pipeline are not needed. Instead the new stack pointer is generated once at the end of the pipeline and written to the register file. The stack pointer is needed for generating the stack-top address in memory. The stack-top address is generated early in the pipeline. Other stack instructions in the pipeline which have not yet incremented the stack pointer are located with a stack valid bit array. The stack valid array indicates the increment or decrement amounts for stack instructions in each pipeline stage. An overall displacement or increment value is computed as the sum of all increments and decrements for stack instructions in the pipeline which have not yet updated the stack pointer. The overall displacement which accounts for all unfinished stack instructions is added to the stack pointer from the register file to generate the stack-top address. Thus the new stack pointer does not have to be generated before the stack memory is accessed.

Pipelined Processor For Executing Repeated String Instructions By Halting Dispatch After Comparision To Pipeline Capacity

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US Patent:
5822602, Oct 13, 1998
Filed:
Jul 23, 1996
Appl. No.:
8/685141
Inventors:
Shalesh Thusoo - Milpitas CA
Assignee:
S3 Incorporated - Santa Clara CA
International Classification:
G06F 938
US Classification:
39580001
Abstract:
A pipelined processor is modified to efficiently process repeated string instructions. A repeated string instruction repeats an iteration a number of times determined by a counter variable stored in a register file. Each iteration includes at least three pipeline flows to perform a load, store, or compare of a character in the string, and to decrement the counter variable. When the last flow of an iteration reaches the execute stage near the end of the pipeline, the current value of the counter variable is compared to the maximum number of iterations which may be present in the pipeline at one time. When the counter variable is equal to the maximum number of iterations, the execute stage signals the decode stage to stop dispatching iterations. The iterations in the pipeline are completed, providing the proper number of iterations. For short strings, the counter value may be less than the maximum number of iterations, and this is signaled to the decode stage, which flushes the pipeline once the current iteration completes.

Debug And Video Queue For Multi-Processor Chip

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US Patent:
5848264, Dec 8, 1998
Filed:
Oct 25, 1996
Appl. No.:
8/740248
Inventors:
Brian R. Baird - Pleasanton CA
David E. Richter - Milpitas CA
Shalesh Thusoo - Milpitas CA
David M. Stark - San Jose CA
James S. Blomgren - San Jose CA
Assignee:
S3 Incorporated - Santa Clara CA
International Classification:
G06F 9455
US Classification:
395500
Abstract:
A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.

Early Instruction-Length Pre-Decode Of Variable-Length Instructions In A Superscalar Processor

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US Patent:
5809272, Sep 15, 1998
Filed:
Nov 29, 1995
Appl. No.:
8/564718
Inventors:
Shalesh Thusoo - Milpitas CA
James S. Blomgren - San Jose CA
Assignee:
Exponential Technology Inc. - San Jose CA
International Classification:
G06F 930
G06F 938
US Classification:
395386
Abstract:
A superscalar processor can dispatch two instructions per clock cycle. The first instruction is decoded from instruction bytes in a large instruction buffer. A secondary instruction buffer is loaded with a copy of the first few bytes of the second instruction to be dispatched in a cycle. In the previous cycle this secondary instruction buffer is used to determine the length of the second instruction dispatched in that previous cycle. That second instruction's length is then used to extract the first bytes of the third instruction, and its length is also determined. The first bytes of the fourth instruction are then located. When both the first and the second instructions are dispatched, the secondary buffer is loaded with the bytes from the fourth instruction. If only the first instruction is dispatched, then the secondary buffer is loaded with the first bytes of the third instruction. Thus the secondary buffer is always loaded with the starting bytes of undispatched instructions.

Reduced Register-Dependency Checking For Paired-Instruction Dispatch In A Superscalar Processor With Partial Register Writes

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US Patent:
5790826, Aug 4, 1998
Filed:
Mar 19, 1996
Appl. No.:
8/618636
Inventors:
Shalesh Thusoo - Milpitas CA
Gene Shen - Mountain View CA
James S. Blomgren - San Jose CA
Assignee:
S3 Incorporated - Santa Clara CA
International Classification:
G06F 938
G06F 928
US Classification:
395392
Abstract:
The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the following instructions' sources, but the destinations of following instructions are not checked with the first instruction's destination. Instead, instructions with destination-destination dependencies are dispatched together as a group. These instructions flow down the pipelines. At the end of the pipelines the destinations are compared. If the destinations match then the results are merged together and written to the register. When instructions write to only a portion of the register, merging ensures that the correct portions of the register are written by the appropriate instructions in the group. Thus older code which performs partial-register writes can benefit from superscalar processing by dispatching the instructions together as a group and then merging the writes together at the end of the pipelines. The dispatch and decode stage, which is often a critical path on the processor, is reduced in complexity by not checking for destination-register dependencies.

Hardware Support For Fast Software Emulation Of Unimplemented Instructions

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US Patent:
5632028, May 20, 1997
Filed:
Mar 3, 1995
Appl. No.:
8/397911
Inventors:
Shalesh Thusoo - Milpitas CA
Farnad Sajjadian - Sunnyvale CA
Jaspal Kohli - Sunnyvale CA
Niteen A. Patkar - Sunnyvale CA
Assignee:
HaL Computer Systems, Inc. - Campbell CA
International Classification:
G06F 300
US Classification:
395500
Abstract:
A system and method provides hardware support for fast software emulation of unimplemented instructions using issue trap logic that determines the instruction type and parameter fields of an unimplemented instruction when an exception is triggered and uses the fields to branch directly to emulation code specific to an unimplemented instruction having the determined instruction type and parameter fields.
Shalesh Thusoo from San Jose, CA, age ~50 Get Report