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Todd Vacca Phones & Addresses

  • 23245 Alpine, Mission Viejo, CA 92692
  • Orange, CA
  • 222 Alpine Estates Dr, Cranston, RI 02921
  • 100 Elena St, Cranston, RI 02920
  • Irvine, CA
  • Wakefield, RI
  • Warwick, RI

Work

Company: International rectifier corp Address: 34 Mauchly, Irvine, CA 92618 Position: Executive director Industries: Semiconductors and Related Devices

Business Records

Name / Title
Company / Classification
Phones & Addresses
Todd Vacca
Executive Director
International Rectifier Corp
Semiconductors and Related Devices
34 Mauchly, Irvine, CA 92618
Todd Vacca
Executive Director
International Rectifier Corp
Semiconductors and Related Devices
34 Mauchly, Irvine, CA 92618

Publications

Us Patents

Dead Time Trimming In A Co-Package Device

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US Patent:
20080224677, Sep 18, 2008
Filed:
Mar 13, 2008
Appl. No.:
12/047796
Inventors:
Kevin Kim - Cerritos CA,
Jason Zhang - Monterey Park CA,
Todd Vacca - Mission Viejo CA,
Assignee:
INTERNATIONAL RECTIFIER CORPORATION - El Segundo CA
International Classification:
G05F 1/10
US Classification:
323282
Abstract:
A method of obtaining an optimized dead time for a synchronous switching power supply comprising a control IC and two series-connected switches, comprising packaging the control IC and the series-connected switches in a co-packaged module; providing a dead time delay circuit within the control IC circuit which has variable dead time; testing the switching power supply; varying the dead time in a defined sequence during the step of testing; monitoring a parameter during testing of the switching power supply as the dead time is varied; determining an optimal dead time based upon monitoring the parameter; and setting the dead time at the optimal dead time.

Intelligent Dead Time Control

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US Patent:
20080298101, Dec 4, 2008
Filed:
Jun 1, 2007
Appl. No.:
11/757181
Inventors:
Seungbeom Kevin Kim - Cerritos CA,
Todd Vacca - Mission Viejo CA,
Jason Zhang - Monterey Park CA,
Assignee:
INTERNATIONAL RECTIFIER CORPORATION - El Segundo CA
International Classification:
H02M 7/04
H02M 7/217
US Classification:
363 84, 363127
Abstract:
A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.
Todd A Vacca from Mission Viejo, CA, age ~50 Get Report